motorola, inc. 1998 6/11/98 motorola semiconductor technical data order this document by mc92314/d advance information 2k integrated dvb-t demodulator the mc92314 is a dvb-t compliant demodulator for 2k transmission mode ac- cording to the etsi specification for digital terrestrial broadcasting (ets 300744). the mc92314 contains all the functionality required to demodulate and decode dvb-t compliant broadcast signals. feature summary ? usable for 8mhz/7mhz/6mhz channels by adjusting the clock rate ? digital i/q separation on-chip ? digital afc on chip ? supports qpsk, 16-qam and 64-qam (non-hierarchical) ? supports all guard interval lengths (1/32, 1/16, 1/8, 1/4) ? automatic locking to any dvb-t guard interval ? accepts 8-bit ttl-compatible twos-complement and offset-binary data input ? provides control signals for agc and adc clock frequency control ? viterbi decoder for dvb convolutional code rates 1/2, 2/3, 3/4, 5/6 and 7/8 ? reed/solomon decoder for dvb reed-solomon code (204,188,8) ?i 2 c serial bus compatible interface (m-bus) for external programming and control ? operating voltage 3.3v ? power requirement 1.7w ? package 160pqfp ordering information device mc92314dh package 160pqfp resb clk clkctln clkctlp mc92314 adcdata[7:0] clken18 agcctln agcctlp trstart trclk trdout[7:0] trerror trvalid figure 1. dvb-t demodulator block diagram this document contains information on a new product. speci?cations and information herein are subject to change without notice.
motorola mc92314_ds - 6/11/98 2 figure 2. pinout of the mc92314 clkctlp reserved (vss) vdd reserved (vss) vss clkctln reserved (vss) vdd reserved (vss) vss scl reserved (vss) vdd reserved (vss) vss sda reserved (vss) vdd reserved (vss) vss clk reserved (vss) vdd reserved (vss) vss mbusid0 reserved (vss) vdd reserved (vss) vss mbusid1 reserved (vss) vdd reserved (open) vss mbusid2 reserved (open) vdd reserved (open) mbusid3 adcdata2 vss reserved (vss) vdd reserved (vss) adcdata1 vss reserved (vss) vdd reserved (vss) adcdata0 vss vdd testmode vss reserved (vss) vdd insync vlock tpslock reserved (open) afclkcb clklckb vss reserved (open) resb vdd reserved (open) vss reserved (open) trerror vdd reserved (open) vss reserved (open) trstart reserved (open) vdd reserved (open) trvalid 160pqfp trclk reserved (open) vss reserved (open) vdd trdout7 reserved (open) vss reserved (open) vdd trdout6 reserved (open) vss reserved (open) vdd trdout5 reserved (open) vss reserved (open) vdd trdout4 reserved (open) vss reserved (open) vdd trdout3 reserved (open) vss reserved (open) vdd trdout2 reserved (open) vss reserved (open) vdd trdout1 reserved (open) vss reserved (open) trdout0 adcdata3 reserved (vss) vss reserved (vss) vdd adcdata4 reserved (vss) vss reserved (vss) vdd adcdata5 reserved (vss) vss reserved (vss) vdd adcdata6 reserved (vss) vss reserved (vss) vdd adcdata7 reserved (vss) vss reserved (vss) vdd (adcdatax) reserved (vss) vss reserved (vss) vdd (adcdatax) vss clken18 reserved (vss) vdd agcctlp reserved (vss) vss reserved (vss) agcctln 20 60 100 140
mc92314_ds - 6/11/98 motorola 3 table 1. mc92314 pin list signal functionality type polty clk common clock input (36.57 mhz) ttl - in high resb reset (asynchronous) ttl - in low clken18 adc data strobe ttl - in high adcdata[7:0] input for samples from adc ttl - in high clkctlp adc clock synchronization loop (+) ttl - out high clkctln adc clock synchronization loop (-) ttl - out low agcctlp analog agc loop (+) ttl - out high agcctln analog agc loop (-) ttl - out low msda i 2 c compatible control bus, data pin ttl - od - mscl i 2 c compatible control bus, clock pin ttl - in high mbusid[3:0]] i 2 c compatible control bus, variable id selector ttl - in high trerror mpeg2 frame error indicator ttl - out high trvalid mpeg2 byte valid indicator ttl - out high trstart mpeg2 sync byte indicator ttl - out high trclk mpeg2 byte clock ttl - out high trdout[7:0] mpeg2 transport stream byte output ttl - out high insync fec frame synchronization status ttl - out high vlock viterbi decoder synchronization status ttl - out high tpslockb tps data valid indicator (inverted) ttl - out high afclck afc lock indicator ttl - out high clklck time synchronization lock indicator ttl - out high
mc92314_ds - 6/11/98 motorola 4 table 2. fec i 2 c register map: addr name type def b7 b6 b5 b4 b3 b2 b1 b0 0 config_vit r/w dap dlt ddec dthr ifs vsync[2:0] 1 threshold r/w thres[4:0] 2 decrement r/w dec[4:0] 3 timeout r/w tim[3:0] 4 avg_period r/w period[3:0] 8 qvallsb r qval[7:0] 9 qvalmsb r qval[14:8] $a sync_vit r vlck $b selectedrate r sr[2:0] $c fifo_state r vff vef $11 aq_thresh r/w sync[2:0] ref[4:0] $12 tr_thresh r/w sync[2:0] ref[4:0] $13 time_count r/w tc[7:0] $18 ber_count r ber[7:0] $19 bad_count r bad[3:0] $1a sync_rs r 00000 rerru deint insync $1f soft_reset r/w gp3 gp2 gp1 gp0 fft rs vit table 3. ofdm i 2 c registers addr name type def b7 b6 b5 b4 b3 b2 b1 b0 0 tps r0 r - s[7:0] 1 tps r1 r - s[15:8] 2 tps r2 r - s[23:16] 3 tps r3 r - s[31:24] 4 tps r4 r - s[39:32] 5 tps r5 r - s[47:40] 6 tps r 6 r - s[55:48] 7 tps r7 r - s[63:56] 8 tps r 8 r - afcl clkl tpsv tpsl s[67:64] 9 tps idx w - idx[7:0] $a reset w - sres $b ofdm r0 w - coderate guard const $c ofdm r1 w $1f 00 0 frot asyn atps afc tsm $d ofdm r2 w $b4 1 afcs agcs 10 uhfi adcm clks
mc92314_ds - 6/11/98 motorola 5 i 2 c programming: the mc92314 2k integrated dvb-t demodulator can be programmed serially over an i 2 c bus protocol. it con- tains two independent i 2 c controllers (one for the fec and one for the ofdm), each with a distinct slave ad- dress in the i 2 c address space. the primary pins mbusid[3:0] can be used to resolve potential slave ad- dress conflicts in an i 2 c based system. the addressing convention is such that an i 2 c slave address is given by the register address space under each i 2 c slave ad- dress is defined for the fec in table 2 and for the ofdm in table 3 . please note that to access any regis- ter, the procedure requires that this register number has to be written into a symbolic address $0 in the first slave access; a second slave access can then proceed with the read or write of the desired register(s). please note, that for the fec a soft reset is only possi- ble in normal operation of the ofdm, i.e. with the tpslockb signal active. operation: the mc92314 2k integrated dvb-t demodulator is preconfigured such that only minimal setup program- ming is required. the rate selection of the fec is auto- matic. if an adc with offset-binary coding is used, ofdm register 2 ($d) must be set accordingly. no fur- ther programming is necessary. the locking process of the mc92314 2k integrated dvb-t demodulator during startup can be observed ex- ternally by monitoring the pins tpslockb, vlock and insync. for error free operation tpslockb should be low, vlock should be high and insync should be high. module selected adr[6:4] adr[3:0] fec 001 mbusid[3:0] ofdm 010 mbusid[3:0]
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